Modeling and Veriication of Isa Implementations Computation Structures Group Memo 400 (a) Modeling and Veriication of Isa Implementations

We propose a method to precisely model implementations of Instruction Set Ar-chitectures (ISA) using term rewriting systems (TRS). Our method facilitates understanding of important micro-architectural diierences without delving into low-level implementation details. More importantly, the use of TRS allows us to prove rigorously the equivalence of diierent implementations. We rst deene AX, a simple RISC ISA, by specifying its operational semantics using a simple in-order execution model. We then give an AX implementation which uses register renaming and permits out-of-order instruction execution. The equivalence of the two models is proved by showing that the two TRS's can simulate each other.